Ferroelectric metal oxide ceramic materials such as lead zirconate titanate (PZT) have been investigated for use in ferroelectric semiconductor memory devices. Other ferroelectric materials, for example strontium bismuth tantalate (SBT), can also be used. FIG. 1 shows a conventional ferroelectric memory cell 105 having a transistor 130 and a ferroelectric capacitor 140. An electrode 142 is coupled to a plateline 170 and another electrode 141 is coupled to the transistor which selectively couples or decouples the capacitor from a bitline 160, depending on the state (active or inactive) of a wordline 150 coupled to the transistor gate.
The ferroelectric memory stores information in the capacitor as remanent polarization. The logic value stored in the memory cell depends on the polarization of the ferroelectric capacitor. To change the polarization of the capacitor, a voltage which is greater than the switching voltage (coercive voltage) needs to be applied across its electrodes. An advantage of the ferroelectric capacitor is that it retains its polarization state after power is removed, resulting in a non-volatile memory cell.
A plurality of memory cells are interconnected by wordlines, bitlines, and platelines to form a memory array. Bitlines are coupled to sense amplifiers to facilitate memory accesses, such as reads and writes. Typically, a sense amplifier is coupled to a pair of bitlines, forming a bitline pair or column of the array. A wordline is coupled to a memory cell from each column, forming a row. The sense amplifiers are coupled to a column decoder and the wordlines are coupled to a row decoder.
During a read memory access, the bitlines of the memory array are precharged to, for example, 0 volts. After the bitlines are precharged, a wordline is selected by the row decoder depending on the row portion of the address, coupling a row of memory cells to respective bitlines. A plateline pulse is then provided on the platelines. The pulse, for example, is about 2.5 V. The pulse creates an electric field across the capacitor of the memory cell of the selected row. This field produces a voltage or a differential read signal on the bitline pair to which the cell is coupled. The differential signal can either be a first or a second voltage value, representing first and second logic level stored in the selected memory cell (e.g., logic 0 or logic 1).
In conventional memory architectures, a row of memory cells are sensed simultaneously (e.g., all bitline pairs of the memory block are read out simultaneously). The column decoder selects one of the sense amplifiers according to the column portion of the address for outputting its information onto, for example, a data line. For architectures with more than one data lines, more than one sense amplifier can be selected simultaneously. One sense amplifier is selected for each data line.
During a memory access, signals on adjacent bitlines of neighboring bitline pairs may have different logic level signals. For example, a bitline may be a logic 1 or logic 0. Also, in some applications, a bitline can have a logic level equal to a reference voltage such as VDD/2. Due to the proximity of the bitline pairs, the signal on one bitline of a bitline pair can affect the signal on an adjacent bitline of another bitline pair. This is referred to as bitline noise coupling effect. For example, two adjacent bitlines from adjacent bitline pairs have different signals (e.g., one has a logic 1 while the other has a logic 0). The one with the logic 1 read signal will pull logic 0 read signal of the other bitline pair higher while the logic 0 read signal will pull the logic 1 read signal of the other bitline pair lower. There may also be a case where one of the adjacent bitlines of two adjacent bitline pairs has either a logic 1 or logic 0 signal while the other has a reference voltage level signal (e.g., VDD/2). The bitline with the reference voltage level would be pulled higher by the adjacent bitline if it has a logic 1 signal or lower if it has a logic 0 signal.
Noise coupling effect of adjacent bitline pairs can reduce read signal margin of the differential signal, which reduces reliability and yields. This problem of noise coupling becomes worse with smaller groundrules. To compensate for the reduced read signal, larger voltage levels may be needed. However, this results in higher power consumption and chip area penalty.
As evidenced from the foregoing discussion, it is desirable to reduce the impact of coupling noise to avoid degrading or reducing the signal margin of a differential signal.